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ASIC Engineering Technical Leader

Cisco Systems, Inc.
United States, California, San Jose
170 W Tasman Dr (Show on map)
Jun 06, 2025

The application window is expected to close on: July 28th, 2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.

Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

  • You will be leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips.
  • Design & implement robust and reusable RTL with CDC/RDC considerations
  • Spec comprehensive CDC/RDC check flows and work with CAD team to implement
  • Review and approve CDC/RDC constraints and waivers
  • Perform static glitch analysis
  • Improve design with prevention of static glitch hazard

Minimum Qualifications

  • Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
  • Prior experience with RTL development on Asynchronous design
  • Prior experience on CDC/RDC concepts and relevant design implementation
  • Prior experience on maintaining CDC/RDC flow and signing-off constraints and waivers
  • Prior work with static glitch hazards and experience on the relevant analysis on synthesis optimized gate netlists

Preferred Qualifications

  • Experience on Static Timing Analysis
  • Experience on VCS simulation SVA (SystemVerilog Assertions)

Why Cisco?

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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