Postdoctoral Appointee, Advanced CMOS Product and Design - Onsite

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The Advanced CMOS Product and Design group is seeking a Postdoctoral Appointee to advance radiation-hardened analog and mixed-signal integrated circuit (IC) design in state-of-the-art foundry process technologies, with an emphasis on Intel 18A/18A-P class (Intel 18AP) nodes and other advanced platforms. The successful candidate will contribute to the end-to-end development of RHBD circuits from architecture and transistor-level design through physical implementation and verification while collaborating closely with experts in radiation effects, device physics, modeling, packaging, test, and system applications.

This role focuses on enabling next-generation, radiation-tolerant microelectronics for national security missions by developing circuit techniques and design methodologies that maintain performance in the presence of TID, SEE (SET/SEU/SEL), and variability, and by maturing these designs toward silicon demonstration. In this position, you will have opportunities to lead technical contributions, publish results, and engage with external partners as appropriate.

• Develop radiation-hardened-by-design analog/mixed-signal circuits (e.g., front ends, references/biasing, regulators, clocks/PLLs, data converters, sensor interfaces, or other mission-relevant macros) in advanced CMOS technologies.
• Perform transistor-level design, simulation, and optimization using industry-standard EDA tools (SPICE-class simulation, mixed-signal verification, and signoff-quality flows).
• Implement layouts and/or oversee physical design activities, including layout-aware design, DRC/LVS, parasitic extraction, EM/IR, and reliability signoff consistent with advanced-node constraints.
• Apply and evaluate RHBD techniques against TID and SEE susceptibility, including upset mitigation strategies, SET-tolerant analog design practices, and robustness to process/voltage/temperature corners.
• Work with radiation-effects subject matter experts to define test structures, radiation characterization plans, and interpretation of radiation test data to improve circuit designs and design rules.
• Collaborate with multi-disciplinary teams on PDK enablement, model validation, design kits, and methodology development to support RHBD design in Intel 18AP-class nodes.
• Support prototype bring-up, debug, and characterization, including bench measurements and correlation to simulation (directly or through close partnership with test engineers).
• Communicate results through technical reports, publications, program reviews, and conference presentations, and contribute to proposal and roadmap activities as needed.
• Collaborate in a multi-disciplinary environment.

Due to the nature of the work, the selected applicant must be able to work onsite.

• PhD in Electrical Engineering. PhD needs to be conferred within the last 5 years.
• Demonstrated expertise in analog or mixed-signal IC design (coursework and/or tapeout experience).
• Experience with circuit simulation and analysis, and familiarity with IC physical design fundamentals.
• Ability to obtain and maintain a DOE Q level security clearance.

• Prior work in radiation effects, RHBD, reliability-aware design, or resilient microelectronics.
• Tapeout experience in advanced nodes (FinFET/GAA helpful) and familiarity with signoff flows.
• Experience with high-speed interfaces, precision analog, low-noise design, data converters, or clocking.
• Experience planning/using silicon measurements to close the loop on models and design methodology.

The Mixed-Signal ASIC/SoC Products Department specializes in developing analog and digital integrated circuits (IC) for a variety of applications that require high reliability, high performance or specialized integrated circuits. The department develops a wide range of Application Specific Integrated Circuits (ASICs) for a variety of government applications. Circuit designs include read-out electronics, data acquisition, information processing, encryption/decryption, radiation-hardened electronics, trusted computing, and control circuit applications. Customers include DOE weapons systems, satellite systems, the intelligence community, Army, Air Force, and commercial industry. Mission success is assured by employing disciplined design methodologies and state-of-the-art computer aided engineering (CAE) tools.

This posting will be open for application submissions for a minimum of three (3) calendar days, including the 'posting date'. Sandia reserves the right to extend the posting date at any time.

Sandia is required by DOE to conduct a pre-employment drug test and background review that includes checks of personal references, credit, law enforcement records, and employment/education verifications. Applicants for employment need to be able to obtain and maintain a DOE Q-level security clearance, which requires U.S. citizenship. If you hold more than one citizenship (i.e., of the U.S. and another country), your ability to obtain a security clearance may be impacted.

Applicants offered employment with Sandia are subject to a federal background investigation to meet the requirements for access to classified information or matter if the duties of the position require a DOE security clearance. Substance abuse or illegal drug use, falsification of information, criminal activity, serious misconduct or other indicators of untrustworthiness can cause a clearance to be denied or terminated by DOE, resulting in the inability to perform the duties assigned and subsequent termination of employment.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status and any other protected class under state or federal law.

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If you have a MedPED and you are selected for an on-site interview at Sandia National Laboratories, there may be additional steps necessary to ensure compliance with NNSA security requirements prior to the interview date.